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Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets Cover

Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets

Open Access
|Jan 2021

Authors

Maciej Kopczyński

Faculty of Computer Science, Bialystok University of Technology

Tomasz Grześ

t.grzes@pb.edu.pl

Faculty of Computer Science, Bialystok University of Technology
Language: English
Page range: 99 - 110
Submitted on: May 5, 2020
|
Accepted on: Nov 5, 2020
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Published on: Jan 29, 2021
Published by: SAN University
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year

© 2021 Maciej Kopczyński, Tomasz Grześ, published by SAN University
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.